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4 VERIFICATION PLAN - SystemVerilog

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4 VERIFICATION PLAN The VERIFICATION plan is a specification for the VERIFICATION effort. It is used to define what is first-time success, how a design is verified, and which testbenches are written1. This chapter addresses the description of a VERIFICATION plan for the UART specified in chapter 2 and with the implementation plan defined in chapter 3. The VERIFICATION plan makes use of suggestions written in Writing Testbenches and Reuse Methodology Manual2. The types of VERIFICATION tests can comprise of compliance, corner case, random, real code, and regression testing.

4 VERIFICATION PLAN The verification plan is a specification for the verification effort. It is used to define what is first-time success, how a design is verified, and which testbenches

  Systemverilog

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