AN136 - PCB Layout Considerations for Non …
Application Note 136AN136-1an136fJune 2012and electrolytic capacitors should not block the air flow to the low profile, surface mount semiconductor compo-nents such as power MOSFETs, PWM controller, etc. To prevent the switching noise from upsetting other analog signals in the system, avoid routing sensitive signal traces underneath the supply if possible. Otherwise, an internal ground plane between the power supply layer and small signal layer is needed for shielding. It is necessary to point out that this power supply loca-tion and board real estate planning should be done at the early design/planning stage of the system.
Application Note 136 AN136-3 an136f Figure 3. Minimize the High di/dt Loop Area in the Synchronous Buck Converter. (a) High di/dt loop (Hot Loop) and its Parasitic PCB Inductors, (b) Layout Example
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