CMOS DEVICE ARCHITECTURE EVOLUTION AND …

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CONFIDENTIALCMOS DEVICE ARCHITECTURE EVOLUTION AND metrology CHALLENGESNAOTO HORIGUCHI, IMECCONFIDENTIALOUTLINE CMOS scaling trend and imec DEVICE roadmap DEVICE scaling and metrology challenges FinFET Horizontal nanowire FET Vertical nanowire FET TFET 2D material devices Summary2CONFIDENTIALCMOS SCALING TRENDTRANSISTOR ARCHITECTURE UNDER PRESSURElog2(#transistors/$)201520132011 2009200714nm20nm28nm40nm65nm90nm20172019 202120232025200510nm7nm5nm7(?)-5nm: Finfet with channel stress and/or Nanowire : Planar DEVICE runs out of steam -electrostatics14nm: Si FinFET DEVICE improved electrostatics, current density, and : Fin/Nanowire devices run out of steamHappy scaling era# transistors per areadoubles every two yearfor same & beyond3D (Vertical) LogicHybrid stackingBeyond CMOSNew compute paradigmsSTCOLess happy scaling eraStill doubles but devicescaling provides diminishing returnsNOWFocus of process technology innovation isScale DEVICE and wireScale basic logic cellsScale (sub-)system func

confidential cmos device architecture evolution and metrology challenges naoto horiguchi, imec

  Devices, Architecture, Challenges, Evolution, Metrology, Device architecture evolution and, Device architecture evolution and metrology challenges