Memory in SystemVerilog
Memory in SystemVerilogProf. Stephen A. EdwardsColumbia UniversitySpring 2015Implementing MemoryMemory = Storage Element Array + AddressingBits are expensiveThey should dumb, cheap, small, and tighly packedBits are numerousCan t just connect a long wire to each oneWilliams TubeCRT-based random access Memory , 1946. Used on theManchester Mark I. 2048 acoustic delay lineUsed in the EDASC, 17 bitsSelectron TubeRCA, 128 bitsFour-dimensional addressingA four-input AND gate ateach bit for selectionMagnetic CoreIBM, Drum Memory1950s & 60s. Secondary Memory ChoicesFamilyProgrammedPersistenceMask ROMat fabrication PROMonce EPROM1000s, UV10 yearsFLASH1000s, block10 yearsEEPROM1000s, byte10 yearsNVRAM 5 yearsSRAM while poweredDRAM 64 msImplementing ROMs0/10Z: notconnected 010111Add. Data000110111010100110102-to-4DecoderA1A 0011110100010Wordline 00Wordline 11Wordline 22Wordline 33Bitline 0D0Bitline 1D1Bitline 2D2Implementing ROMs0/10Z: notconnected 010111Add.
0/1 0 Z: “not connected” 0 1 0 1 1 1 ... Introduction to CMOS VLSI Design. Addison-Wesley, 2010. Intel’s 2102 SRAM, 1024 1 bit, 1972. 2102 Block Diagram. SRAM Timing A12 A11 A2 A1 A0 CS2 D7 D6 D1 D0..... CS1 WE OE 6264 8K 8 SRAM CS1 CS2 WE OE Addr 1 …
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