Pipelining Basic 5 Stage PipelineBasic 5 Stage Pipeline

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EE 357 Unit 18EE 357 Unit 18Basic Pipelining Techniques Mark Redekopp, All rights reservedSingle & Multi-Cycle PerformanceSingle & MultiCycle PerformanceSingleCycle CPUMultiCycle CPUSingle-Cycle CPU Each piece of the datapath requires only a small period of thll i ttiMulti-Cycle CPU Sharing resources allows for compact logic design but in ddiffdthe overall instruction execution (clock cycle) time yielding low utilization of the HW s actual capabilitiesmodern design we can afford replicated structures if needed Each instruction still requires lltltHW s actual capabilities several cycles to complete+Read Reg. 1 #Sh. Lef t + Reg. 2 #WriteReg. #Write DataRead data 1Read data 0155 Mark Redekopp, All rights reservedRegister FileaaSign Extend1D-CacheeadDataWrite Data11632PipeliningPipelining Combines elements of both designsg Datapath of ______________ CPU w/ separate resources Datapath broken into _________ with temporary registers between stagesstages _________ clock cycle A single instruction requires CPI = nS stem can achie e CPI System can achieve CPI = _________ Overlapping Multiple Instructions (separate instruction in each Stage at once)Inst.

Basic 5 Stage PipelineBasic 5 Stage Pipeline • Same structure as single cycle but now broken into 5 stages • Pipeline stage registersPipeline stage registers act as temp registers storing intermediateact as temp. registers storing intermediate results and thus allowing previous stage to be reused for another instruction

  Pipeline