Software Developer Guide - Xilinx
Zynq UltraScale+ MPSoCSoftware Developer GuideUG1137 ( ) July 1, 2020Revision HistoryThe following table shows the revision history for this Summary07/01/2020 Version 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags to add a new 12: ResetUpdated RPU Subsystem Restart for RPU only restartsupport E: XilSecure Library Additional H: XilFPGA Library Additional Version Embedded FlowUpdated SDK flows to Vitis Embedded Flow throughout Version 4: Software StackUpdated Multimedia Stack 7: System Boot and ConfigurationUpdated Miscellaneous FunctionsChapter 10: Platform Management Unit FirmwareAdded CSU/PMU Register Access and updated PMUFirmware Build FlagsChapter 11: Power Management FrameworkUpdated Sub-system Power ManagementAdded appendix01/18/2019 Version 2: Programming View of Zynq UltraScale+ MPSoCDevicesUpdated Boot Modes and System-Level Protections sectio
CSU and Wake UP Mechanisms. Added Pre-Boot Sequence . Chapter 8: Security Features Updated chapter and removed Encryption Key Types and Key Registers table. Chapter 9: Platform Management Added Power Management Framework and updated PMU Firmware DMA Removed chapter System Coherency Removed chapter Chapter 16: Boot Image Creation …
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