Software Developer Guide - Xilinx
Zynq UltraScale+ MPSoCSoftware Developer GuideUG1137 ( ) July 1, 2020Revision HistoryThe following table shows the revision history for this Summary07/01/2020 Version 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags to add a new 12: ResetUpdated RPU Subsystem Restart for RPU only restartsupport E: XilSecure Library Additional H: XilFPGA Library Additional Version Embedded FlowUpdated SDK flows to Vitis Embedded Flow throughout Version 4: Software StackUpdated Multimedia Stack 7: System Boot and ConfigurationUpdated Miscellaneous FunctionsChapter 10: Platform Management Unit FirmwareAdded CSU/PMU Register Access and updated PMUFirmware Build FlagsChapter 11: Power Management FrameworkUpdated Sub-system Power ManagementAdded appendix01/18/2019 Version 2: Programming View of Zynq UltraScale+ MPSoCDevicesUpdated Boot Modes and System-Level Protections sectionsChapter 3: Development ToolsAdded Device Tree GeneratorChapter 4: Software StackRemoved XilRSA referencesChapter 8: Security FeaturesUpdated Configuring XMPU RegistersChapter 9: Platform ManagementUpdated Power Management FrameworkChapter 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags, FPD WDT, and PMUFirmware Memory Layout and FootprintChapter 12: ResetUpdated Warm Restart with a note about on-chip memory(OCM)Chapter 16: Boot Image CreationRemoved content and updated the chapter with a s
Updated Encryption and Authentication sections. Chapter 16: Boot Image Creation Added parameters and descriptions in Table 16-1. Added Boot Image Format. Added additional bit descriptions in Table 16-9. Added Appendixes for OS & Libraries content (Appendixes A-K). 12/15/2016 Version 3.0 Chapter 1: About This Guide Updated Introduction
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