Tutorial on Digital Phase-Locked Loops - CppSim
Tutorial onDigital Phase-Locked LoopsCICC 2009Michael H. PerrottSeptember 2009Copyright 2009 by Michael H. PerrottWhy Are Digital Phase-Locked Loops Interesting? Performance is important-Phase noise can limit wireless transceiver performance-Jitter can be a problem for Digital processors The standard analog PLL implementation is problematic in many applications-Analog building blocks on a mostly Digital chip pose design and verification challenges-The cost of implementation is becoming too high ...Can Digital Phase-Locked Loops offer excellent performance with a lower cost of implementation?Just Enough PLL Background.
M.H. Perrott 20 Leveraging Dithering for Fine Control of DCO Increase resolution by Σ−Δdithering of fine cap array Reduce noise from dithering by-Using small unit caps in the fine cap array-Increasing the dithering frequency (defined as 1/Tc) We will assume 1/T c = M/T (i.e. M times reference frequency) Varactor Varactor Coarse Control Fine …
Download Tutorial on Digital Phase-Locked Loops - CppSim
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: