MIPS Pipeline - Cornell University

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Hakim WeatherspoonCS 3410, Spring 2012Computer ScienceCornell UniversityMIPS PipelineSee P&H Chapter ProcessoraluPCimmmemorymemorydindoutaddr targetoffsetcmpcontrol=?new pcregisterfileinstextend+4+4Review: Single cycle processor3What determines performance of Processor?A) Critical PathB) Clock Cycle TimeC) Cycles Per Instruction (CPI)D) All of the aboveE) None of the above4Review: Single Cycle ProcessorAdvantages Single Cycle per instruction make logic and clock simpleDisadvantages Since instructions take different time to finish, memory and functional unit are not efficiently utilized.

Five stage “RISC” load‐store architecture 1.Instruction fetch (IF) –get instruction from memory, increment PC 2.Instruction Decode (ID) –translate opcodeinto control signals and read registers 3.Execute (EX) –perform ALU operation, compute jump/branch targets ... Collaboration, Late, Re‐grading Policies

  Late, Stage, Pipeline, Imps, Mips pipeline