Transcription of 10 Gigabit Ethernet Subsystem v3 - Xilinx
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10 Gigabit Ethernet Subsystem v3 - Xilinx
10 gigabit ethernet subsystem Product Guide Vivado Design Suite PG157 February 4, 2021. Table of Contents Chapter 1: Overview Feature Summary.. 8. Applications .. 9. Unsupported Features.. 10. Licensing and Ordering .. 10. Chapter 2: Product Specification Standards .. 13. Performance.. 13. Resource Utilization.. 13. Latency .. 13. Port Descriptions .. 15. Register Space .. 50. Chapter 3: Designing with the Subsystem Clocking.. 89. Resets .. 89. 7 Series Clocking and Shared Logic .. 90. UltraScale Device Clocking and Shared Logic Using the RX Elastic Buffer .. 92. UltraScale Device Clocking and Shared Logic Omitting the RX Elastic Buffer .. 97. Shared Logic for 7 Series IEEE 1588 Support .. 99. Ethernet Protocol Description.. 101. Connecting the Data Interfaces.. 107. IEEE 1588 Timestamping .. 130. Connecting the Management Interface .. 139. IEEE Flow Control.
The 10G Ethernet subsystem provides 10 Gb/s Ethernet MAC, Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) transmit and receive functionality over an AXI4-Stream interface. The subsystem is designed to interface with a 10GBASE-R
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