Transcription of 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On …
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2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On …
MSPS, 24-Bit, 100 dB. Sigma-Delta ADC with On- chip buffer ad7760 . FEATURES FUNCTIONAL BLOCK DIAGRAM. 120 dB dynamic range at 78 kHz output data rate VIN VIN+. 100 dB dynamic range at MHz output data rate 112 dB SNR at 78 kHz output data rate DIFF. MULTIBIT AVDD1. - . 100 dB SNR at MHz output data rate MODULATOR AVDD2. AVDD3. MHz maximum fully filtered output word rate VREF+. BUF RECONSTRUCTION AVDD4. Programmable oversampling rate (8 to 256 ). DECAPA/B. Fully differential modulator input RBIAS. On- chip differential amplifier for signal buffering ad7760 PROGRAMMABLE AGND. DECIMATION. Low-pass finite impulse response (FIR) filter with default or VDRIVE. user-programmable coefficients MCLK. CONTROL LOGIC DVDD. I/O. Modulator output mode SYNC OFFSET AND GAIN DGND. REGISTERS. Overrange alert bit RESET FIR FILTER. ENGINE. Digital offset and gain correction registers 04975-001. Filter bypass modes CS RD/WR DRDY DB0 TO DB15. Low power and power-down modes Figure 1.
2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer AD7760 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable.
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