Transcription of 4 VERIFICATION PLAN
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4 VERIFICATION PLAN
4 VERIFICATION PLAN The VERIFICATION plan is a specification for the VERIFICATION effort. It is used to define what is first-time success, how a design is verified, and which testbenches are written1. This chapter addresses the description of a VERIFICATION plan for the UART specified in chapter 2 and with the implementation plan defined in chapter 3. The VERIFICATION plan makes use of suggestions written in Writing Testbenches and Reuse Methodology Manual2. The types of VERIFICATION tests can comprise of compliance, corner case, random, real code, and regression testing. In addition to the VERIFICATION plan, this chapter provides a discussion on VERIFICATION languages, general VERIFICATION requirements for components, and the rationale for the selection of VHDL for this book.
effective application of this methodology provides four essential capabilities to help break through the verification bottleneck: 1. Automates the verification process, reducing by as much as four times the amount of manual work needed to develop the verification environment and tests;
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