Transcription of A Cloud-Scale Acceleration Architecture
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A Cloud-Scale Acceleration Architecture
A Cloud-Scale Acceleration ArchitectureAdrian M. CaulfieldEric S. ChungAndrew PutnamHari AngepatJeremy FowersMichael HaselmanStephen HeilMatt HumphreyPuneet KaurJoo-Young KimDaniel LoTodd MassengillKalin OvtcharovMichael PapamichaelLisa WoodsSitaram LankaDerek ChiouDoug BurgerMicrosoft CorporationAbstract Hyperscale datacenter providers have struggled tobalance the growing need for specialized hardware (efficiency)with the economic benefits of homogeneity (manageability). Inthis paper we propose a new cloud Architecture that usesreconfigurable logic to accelerate both network plane func-tions and applications. This Configurable cloud architectureplaces a layer of reconfigurable logic (FPGAs) between thenetwork switches and the servers, enabling network flows to beprogrammably transformed at line rate, enabling accelerationof local applications running on the server, and enabling theFPGAs to communicate directly, at datacenter scale , to harvestremote FPGAs unused by their local servers.
Altera Stratix V D5 FPGA. 256 Mb Config Flash. U S B. 4 GB DDR3 -1600. 40Gb QSFP Network to TOR. USB to JTAG µC. to NIC. 4 lanes @ 10.3125 Gbps. 4 lanes @ 10.3125 Gbps. 72 bits QSPI (with ECC) PCIe Mezanine Connector. PCIe Gen3 x8. PCIe Gen3 x8. Temp, power, LEDs. I2C. Fig. 2. Block diagram of the major components of the accelerator board. of ...
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