always @(posedge clk ) begin - MIT OpenCourseWare

WA1 Digital Design Using verilog ) begin modulebeta(clk,reset,irq,.. Input[31:0]mem_data; endmoduleIf(done)$finish; Figures by MIT OCW. PC+4+4*SXT(C) ASEL 01 Data Memory RD WD Adr R/W WDSEL 0 1 2 Rc: <25:21> 01XP PC JT +4 Instruction Memory A D Rb: <15:11> Ra: <20:16> RA2 SELRc: <25:21> + Register FileRA1 RA2 RD1 RD2 BSEL 01 C: SXT(<15:0>)Z ALUA B JTWA WD WE ALUFNC ontrolLogic Z ASEL BSEL PCSEL RA2 SEL WDSEL ALUFN Wr PC+4 0 1 Wr 01234 XAdrILLOP WASEL WASEL IRQ WERF WERF 00 PCSEL L02 verilog Spring 2005 02/04/05 always @( posedge clkassign pcinc = pc + 4; for (i=0; i < 31; i = i+1) begin Hardware Description Languages In the beginning designs involved just a few gates, and thus it was possible to verify these circuits on paper or with breadboards Spring 2005 02/04/05 L02 verilog 2 Hardware Description Languages As designs grew larger and more complex, designers began using gate-level models described in a Hardware Description Language to help with verification before fabrication Spring 2005 02/04/05 L02 verilog 3 Hardware Description Languages When designers began working on 100,000 gate desi)

separate behavior from implementation at various levels of abstraction HDLs do this with modules and interfaces Figure by MIT OCW. 6.884 – Spring 2005 02/04/05 L02 – Verilog 6 . ... Design is composed of modules which have just one implementation Gate-level, dataflow, and behavioral modeling. Synthesizable subset.

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