Transcription of always @(posedge clk ) begin - MIT OpenCourseWare
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always @(posedge clk ) begin - MIT OpenCourseWare
WA1 digital Design Using verilog ) begin modulebeta(clk,reset,irq,.. Input[31:0]mem_data; endmoduleIf(done)$finish; Figures by MIT OCW. PC+4+4*SXT(C) ASEL 01 Data Memory RD WD Adr R/W WDSEL 0 1 2 Rc: <25:21> 01XP PC JT +4 Instruction Memory A D Rb: <15:11> Ra: <20:16> RA2 SELRc: <25:21> + Register FileRA1 RA2 RD1 RD2 BSEL 01 C: SXT(<15:0>)Z ALUA B JTWA WD WE ALUFNC ontrolLogic Z ASEL BSEL PCSEL RA2 SEL WDSEL ALUFN Wr PC+4 0 1 Wr 01234 XAdrILLOP WASEL WASEL IRQ WERF WERF 00 PCSEL L02 verilog Spring 2005 02/04/05 always @( posedge clkassign pcinc = pc + 4; for (i=0; i < 31; i = i+1) begin Hardware Description Languages In the beginning designs involved just a few gates, and thus it was possible to verify these circuits on paper or with breadboards Spring 2005 02/04/05 L02 verilog 2 Hardware Description Languages As designs grew larger and more complex, designers began using gate-level models described in a Hardware Description Language to help with verification before fabrication Spring 2005 02/04/05 L02 verilog 3 Hardware Description Languages When designers began working on 100,000 gate designs, these gate-level models were too low-level for the initial functional specification and early high-level design exploration Spring 2005 02/04/05 L02 verilog 4 Hardware Description Languages Designers again t)
Digital Design Using Verilog ) begin mo d u l e b e t a (c l k, r e s e t, i r q, … I n p u t [3 1: 0] m e m _ d a t a; e n d m o d u l e I f (d o n e) $ f i n i s h; Figures by MIT OCW. P C + 4 + 4 * S X T ( C ) A E L 0 1 D a ta M e m o r y R D ... modules and interfaces Figure by MIT OCW. 6.884 – Spring 2005 02/04/05 L02 – Verilog 6 .
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