Transcription of Aurora 64B/66B v11 - Xilinx
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Aurora 64B/66B v11 - Xilinx
Aurora 64B/66B LogiCORE IP Product Guide Vivado Design Suite PG074 April 4, 2018. Table of Contents IP Facts Chapter 1: Overview Applications .. 6. Unsupported Features.. 7. Licensing and Ordering .. 7. Chapter 2: Product Specification Performance.. 9. Resource Utilization.. 11. Port Descriptions .. 11. Chapter 3: Designing with the Core General Design Guidelines .. 61. Clocking.. 62. Reset and Power Down .. 66. Shared Logic .. 73. Using CRC .. 75. Hot Plug Logic.. 75. Clock Compensation Logic.. 76. Using Little Endian Support .. 77. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 78. Constraining the Core .. 95. Simulation .. 99. Synthesis and Implementation .. 100. Chapter 5: Example Design Directory and File Contents.. 101. Quick Start Example Design .. 101. Detailed Example Design.. 103. Aurora 64B/66B Send Feedback 2.
Provided by Xilinx at the Xilinx Support web page Notes: 1. For a complete list of supported devices and configurations, see the Vivado IP catalog and associated FPGA Datasheets. 2. For more information, see the Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref1] and Kintex UltraScale FPGAs Data Sheet: DC and AC
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