Transcription of AXI Block RAM (BRAM) Controller v4 - Xilinx
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AXI Block RAM (BRAM) Controller v4 - Xilinx
AXI Block RAM (BRAM). Controller LogiCORE IP Product Guide Vivado Design Suite PG078 October 5, 2016. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 8. Applications .. 10. Licensing and Ordering Information .. 11. Chapter 2: Product Specification Standards .. 12. Performance.. 13. Resource Utilization.. 14. Port Descriptions .. 14. Register Space .. 22. Chapter 3: Designing with the Core General Design Guidelines .. 34. Clocking.. 69. Resets .. 69. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 70. Constraining the Core .. 73. Simulation .. 74. Synthesis and Implementation .. 74. Chapter 5: Test Bench Messages and Warnings .. 76. Chapter 6: Example Design Appendix A: Migrating and Upgrading Migrating to the Vivado Design Suite.. 78. Upgrading in the Vivado Design Suite.
are accessible via an additional AXI4-Lite cont rol interface on the AX I BRAM Controller core. The ECC functionality can be enabled regardless of dual or single port BRAM access. ECC is enabled by configuring the design parameter, C_ ECC = 1. The ECC is available only when the BRAM block is configured to a 32-, 64-, or 128-bit data width.
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