Transcription of AXI Block RAM (BRAM) Controller v4 - Xilinx
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AXI Block RAM (BRAM) Controller v4 - Xilinx
AXI Block RAM (BRAM). Controller LogiCORE IP Product Guide Vivado Design Suite PG078 October 5, 2016. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 8. Applications .. 10. Licensing and Ordering Information .. 11. Chapter 2: Product Specification Standards .. 12. Performance.. 13. Resource Utilization.. 14. Port Descriptions .. 14. Register Space .. 22. Chapter 3: Designing with the Core General Design Guidelines .. 34. Clocking.. 69. Resets .. 69. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 70. Constraining the Core .. 73. Simulation .. 74. Synthesis and Implementation .. 74. Chapter 5: Test Bench Messages and Warnings .. 76. Chapter 6: Example Design Appendix A: Migrating and Upgrading Migrating to the Vivado Design Suite.. 78. Upgrading in the Vivado Design Suite .. 78. LogiCORE IP AXI BRAM Controller Send Feedback 2.
The AXI BRAM Controller IP supports a minimum depth of 512 bytes. Any depth that is less than 512 gets reset to 512 bytes. ECC Support ECC support can be enabled in the AXI BRAM Controller IP core by setting the design parameter, C_ECC = 1. ECC is only supported for BRAM data widths of 32-, 64-, or 128-bit configurations.
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