Transcription of AXI Block RAM (BRAM) Controller v4 - Xilinx
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AXI Block RAM (BRAM) Controller v4 - Xilinx
AXI Block RAM (BRAM). Controller LogiCORE IP Product Guide Vivado Design Suite PG078 October 5, 2016. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 8. Applications .. 10. Licensing and Ordering Information .. 11. Chapter 2: Product Specification Standards .. 12. Performance.. 13. Resource Utilization.. 14. Port Descriptions .. 14. Register Space .. 22. Chapter 3: Designing with the Core General Design Guidelines .. 34. Clocking.. 69. Resets .. 69. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 70. Constraining the Core .. 73. Simulation .. 74. Synthesis and Implementation .. 74. Chapter 5: Test Bench Messages and Warnings.
LogiCORE IP AXI BRAM Controller v4.0 www.xilinx.com 4 PG078 October 5, 2016 Product Specification Introduction The LogiCORE™ IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite. The core is designed as an AXI Endpoint slave IP for integration with the AXI interconnect and system master devices to
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