Transcription of AXI DataMover v5 - Xilinx
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AXI DataMover v5 - Xilinx
AXI DataMover IP Product GuideVivado Design SuitePG022 April 5, 2017 AXI DataMover April 5, of ContentsIP FactsChapter 1: OverviewFeature Summary.. 7 Applications .. 8 Unsupported Features .. 8 Licensing and Ordering Information .. 9 Chapter 2: Product SpecificationPerformance .. 10 Resource Utilization .. 12 Port Descriptions .. 14 Design Information .. 18 Chapter 3: Designing with the CoreClocking.. 36 Resets .. 36 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 37 Constraining the Core.
data transport and protocol conversion. The function is intended to be a standalone core for custom designs. Features • AXI4 Compliant • Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits • Primary AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits • Parameterized Memory Map Burst Lengths
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