Transcription of AXI DMA v7 - Xilinx
{{id}} {{{paragraph}}}
Example: marketing
AXI DMA v7 - Xilinx
axi dma LogiCORE IP Product Guide Vivado Design Suite PG021 June 14, 2019. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 6. Applications .. 7. Licensing and Ordering .. 7. Chapter 2: Product Specification Performance.. 8. Resource Utilization.. 10. Port Descriptions .. 10. Register Space .. 11. Scatter Gather Descriptor .. 38. Multichannel DMA Support .. 56. Chapter 3: Designing with the Core Typical System Interconnect .. 68. Clocking.. 69. Resets .. 70. Programming Sequence.. 70. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 75. Constraining the Core .. 83. Simulation .. 84. Synthesis and Implementation .. 84. Chapter 5: Example Design Implementing the Example Design .. 87. Simulating the Example Design.. 88. Test Bench for the Example Design .. 89. LogiCORE IP axi dma Send Feedback 2. PG021 June 14, 2019 Appendix A: Upgrading Migrating to the Vivado Design Suite.. 90. Upgrading in the Vivado Design Suite .. 90. Appendix B: Debugging Finding Help on.
LogiCORE IP AXI DMA v7.1 4 PG021 June 14, 2019 www.xilinx.com Product Specification PG021 June 14, 2019 Introduction The Xilinx® LogiCORE™ IP AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI DMA provides high-bandwidth direct memory access between memory and
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: