Transcription of AXI DMA v7 - Xilinx
{{id}} {{{paragraph}}}
AXI DMA LogiCORE IP Product Guide Vivado Design Suite PG021 June 14, 2019. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 6. Applications .. 7. Licensing and Ordering .. 7. Chapter 2: Product Specification Performance.. 8. Resource Utilization.. 10. Port Descriptions .. 10. Register Space .. 11. Scatter Gather Descriptor .. 38. Multichannel DMA Support .. 56. Chapter 3: Designing with the Core Typical System Interconnect .. 68. Clocking.. 69. Resets .. 70. Programming Sequence.. 70. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 75. Constraining the Core .. 83. Simulation .. 84. Synthesis and Implementation .. 84. Chapter 5: Example Design Implementing the Example Design .. 87. Simulating the Example Design.. 88. Test Bench for the Example Design .. 89. LogiCORE IP AXI DMA Send Feedback 2.
Primary high-speed DMA data movement between system memory and stream target is through the AXI4 Read Master to AXI4 memory-mapped to stream (MM2S) Master, and AXI stream to memory-mapped (S2MM) Slave to AXI4 Write Master. AXI DMA also enables up to 16 multiple channels of data movement on both MM2S and S2MM paths in scatter/gather mode.
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document:
{{id}} {{{paragraph}}}