AXI IIC Bus Interface v2 - Xilinx

AXI IIC Bus Interface IP Product GuideVivado design SuitePG090 October 5, 2016 AXI IIC Bus Interface October 5, of ContentsIP FactsChapter 1: OverviewFunctional Description.. 5 Applications .. 7 Licensing and Ordering Information .. 7 Chapter 2: Product SpecificationStandards .. 8 Performance .. 8 Resource Utilization .. 9I/O Signals .. 10 Register Space .. 11 Chapter 3: Designing with the CoreIIC Protocol and Electrical Characteristics .. 29 Interrupts .. 32 Programming Sequence.. 33 Timing Diagrams.

Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3]. Table 2-1 shows the results of the characterization runs. Note: Performance numbers for UltraScale™ architecture and Zynq®-7000 All Programmable SoC devices are expected to be similar to 7 series device numbers. Table 2-1: Maximum Frequencies Family Speed Grade FMax (MHz)

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