Transcription of AXI IIC Bus Interface v2 - Xilinx
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AXI IIC Bus Interface v2 - Xilinx
AXI IIC Bus Interface IP Product GuideVivado Design SuitePG090 October 5, 2016 AXI IIC Bus Interface October 5, of ContentsIP FactsChapter 1: OverviewFunctional Description.. 5 Applications .. 7 Licensing and Ordering Information .. 7 Chapter 2: Product SpecificationStandards .. 8 Performance .. 8 resource Utilization .. 9I/O Signals .. 10 Register Space .. 11 Chapter 3: Designing with the CoreIIC Protocol and Electrical Characteristics .. 29 Interrupts .. 32 Programming Sequence.. 33 Timing Diagrams .. 39 Clocking.. 41 Resets.
UltraScale™ Architecture, Zynq®-7000 All Programmable SoC, 7 Series Supported User Interfaces AXI4-Lite Resources See Table 2-2. Provided with Core Design Files VHDL Example Design VHDL Test Bench VHDL Constraints File XDC delivered with IP generation. Simulation Model None Supported S/W Driver(2) Standalone and Linux Tested Design Tools(3 ...
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