Transcription of AXI IIC Bus Interface v2 - Xilinx
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AXI IIC Bus Interface v2 - Xilinx
AXI IIC Bus Interface IP Product GuideVivado Design SuitePG090 October 5, 2016 AXI IIC Bus Interface October 5, of ContentsIP FactsChapter 1: OverviewFunctional Description.. 5 Applications .. 7 Licensing and Ordering Information .. 7 Chapter 2: Product SpecificationStandards .. 8 Performance .. 8 Resource Utilization .. 9I/O Signals .. 10 Register Space .. 11 Chapter 3: Designing with the CoreIIC Protocol and Electrical Characteristics .. 29 Interrupts .. 32 Programming Sequence.. 33 Timing Diagrams .. 39 Clocking.. 41 Resets .. 41 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 42 Constraining the Core .. 46 Simulation .. 47 Synthesis and Implementation .. 47 Chapter 5: Example DesignOverview .. 48 Implementing the Example Design .. 49 Simulating the Example Design.. 50 Send FeedbackAXI IIC Bus Interface October 5, 6: Test BenchAppendix A: Migrating and UpgradingMigrating to the Vivado Design Suite.
see the LogiCORE™ IP AXI4-Lite IPIF Product Guide (PG155) [Ref 2]. • Interrupt Control – This module gets the interrupt status from the AXI IIC and generates an interrupt to the host. • Registers Interface – This module contains Control and Status registers. It also provides an option to access TX FIFO and RX FIFO.
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