Transcription of AXI Interconnect v2 - Xilinx
{{id}} {{{paragraph}}}
Example: bankruptcy
AXI Interconnect v2 - Xilinx
AXI Interconnect IP Product GuideVivado Design SuitePG059 December 20, 2017 AXI Interconnect Product Guide December 20, of ContentsIP FactsChapter1: OverviewAXI Infrastructure Cores .. 5 Feature Summary.. 6 Applications .. 9 AXI Interconnect Core Limitations .. 9 Licensing and Ordering .. 10 Chapter2: Product SpecificationUse Models.. 12 Standards .. 17 Latency .. 17 Maximum Performance.. 20 Resource Utilization.. 34 Port Descriptions .. 52 Register Space .. 70 Chapter3: Designing with the CoreAXI Interconnect Core Functionality.. 71 Design Parameters.. 96 Clocking.. 108 Resets .. 108 Chapter4: Design Flow StepsCustomizing and Generating the Core .. 110 Constraining the Core .. 152 Simulation .. 154 Synthesis and Implementation.. 155 Send FeedbackAXI Interconnect Product Guide December 20, : Example DesignAppendixA: UpgradingMigration from CORE Generator System AXI Interconnect Core.
The Xilinx® LogiCORE™ IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. Note:The AXI Interconnect core is intended for memory-mapped transfers only. For AXI4-Stream transfers, see the AXI4-Stream Infrastructure IP Suite LogiCORE IP Product Guide (PG085) [Ref1]. Features
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: