Transcription of AXI Interconnect v2 - Xilinx
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AXI Interconnect v2 - Xilinx
AXI Interconnect IP Product GuideVivado Design SuitePG059 December 20, 2017 AXI Interconnect Product Guide December 20, of ContentsIP FactsChapter1: OverviewAXI Infrastructure Cores .. 5 Feature Summary.. 6 Applications .. 9 AXI Interconnect Core Limitations .. 9 Licensing and Ordering .. 10 Chapter2: Product SpecificationUse Models.. 12 Standards .. 17 Latency .. 17 Maximum Performance.. 20 resource Utilization.. 34 Port Descriptions .. 52 Register Space .. 70 Chapter3: Designing with the CoreAXI Interconnect Core Functionality.. 71 Design Parameters.. 96 Clocking.. 108 Resets .. 108 Chapter4: Design Flow StepsCustomizing and Generating the Core .. 110 Constraining the Core .. 152 Simulation .. 154 Synthesis and Implementation.. 155 Send FeedbackAXI Interconnect Product Guide December 20, : Example DesignAppendixA: UpgradingMigration from CORE Generator System AXI Interconnect Core.
- Minimizes resource utilization. • Supports multiple outstanding transactions (crossbar mode) ° Supports connected masters with multiple reordering depth (ID threads). ° Supports up to 32-bit wide ID signals with varying ID width per connected master. ° Supports write response re-ordering, Read data re-ordering, and Read Data interleaving.
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