Transcription of AXI Interrupt Controller (INTC) v4 - Xilinx
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AXI Interrupt Controller (INTC) IP Product GuideVivado Design Suite PG099 July 15, 2021 AXI INTC Product Guide2PG099 July 15, of ContentsIP FactsChapter 1: OverviewFeature Summary.. 6 Licensing and Ordering .. 8 chapter 2: Product SpecificationPerformance.. 9 Resource Utilization.. 9 Port Descriptions .. 9 Register Space .. 15 chapter 3: Designing with the CoreClocking .. 28 Resets .. 28 Programming Sequence.. 28 Cascade Mode Interrupt .. 29 Timing Diagrams .. 33 Interrupt Input Requirements.. 34 chapter 4: Design Flow StepsCustomizing and Generating the Core .. 35 Constraining the Core .. 42 Simulation .. 43 Synthesis and Implementation.
AXI INTC v4.1 Product Guide 6 PG099 July 15, 2021 www.xilinx.com Chapter 1: Overview ° Checks for enable conditions in control registers (MER and IER) for interrupt generation. ° Resets the interrupt after acknowledge. ° Writes the vector address of the active interrupt in IVR register and enables the IPR register for pending interrupts. Feature Summary ...
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