Transcription of AXI Interrupt Controller (INTC) v4 - Xilinx
{{id}} {{{paragraph}}}
Example: bankruptcy
AXI Interrupt Controller (INTC) v4 - Xilinx
AXI Interrupt Controller (INTC) IP Product GuideVivado Design Suite PG099 July 15, 2021 AXI INTC Product Guide2PG099 July 15, of ContentsIP FactsChapter 1: OverviewFeature Summary.. 6 Licensing and Ordering .. 8 Chapter 2: Product SpecificationPerformance.. 9 Resource Utilization.. 9 Port Descriptions .. 9 Register Space .. 15 Chapter 3: Designing with the CoreClocking .. 28 Resets .. 28 Programming Sequence.. 28 Cascade Mode Interrupt .. 29 Timing Diagrams .. 33 Interrupt Input Requirements.
IAR SIE 1 CIE 1 IVR MER Int Det Irq Gen 1 IMR ILR1 IVAR 1 ... intended for inter-processor interrupts in multi-processor systems. These interrupts are triggered by software writing to the Interrupt Status Register. Nested Interrupts The core provides support for nested interrupts, by implementing an Interrupt Level ...
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: