Transcription of AXI Traffic Generator v3 - Xilinx
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AXI Traffic Generator v3 - Xilinx
AXI Traffic Generator IP Product GuideVivado Design SuitePG125 April 4, 2018 AXI Traffic Generator April 4, of ContentsIP FactsChapter1: OverviewModes Description.. 7 Programming Sequence.. 27 Applications .. 29 Licensing and Ordering .. 31 Chapter2: Product SpecificationPerformance.. 32 Resource Utilization.. 35 Port Descriptions .. 35 Register Space .. 38 Chapter3: Designing with the CoreClocking.. 49 Resets .. 49 Chapter4: Design Flow StepsCustomizing and Generating the Core .. 50 Constraining the Core .. 65 Simulation .. 66 Synthesis and Implementation.. 66 Chapter5: Example DesignImplementing the Example Design.. 68 Simulating the Example Design.. 69 Chapter6: Test BenchExample Sequences for Custom Mode.. 71 Example Sequences for High Level Traffic (Video, PCIe, Ethernet, USB) Modes.. 72 Example Sequences for High Level Traffic (Data) Mode.
AXI Traffic Generator v3.0 6 PG125 April 4, 2018 www.xilinx.com Chapter 1: Overview Figure1-1 shows the top-level AXI4 Traffic Generator block diagram.
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