Transcription of AXI UART Lite v2 - Xilinx
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AXI UART Lite v2 - Xilinx
AXI UART Lite IP Product GuideVivado Design SuitePG142 April 5, 2017 AXI UART Lite April 5, 2017 Table of ContentsIP FactsChapter 1: OverviewFeature Summary.. 6 Licensing and Ordering Information .. 6 Chapter 2: Product SpecificationPerformance .. 7 Resource Utilization .. 8 Port Descriptions .. 8 Register Space .. 9 Chapter 3: Designing with the CoreClocking.. 13 Resets .. 13 Programming Sequence.. 13 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 14 Constraining the Core .. 16 Simulation .. 17 Synthesis and Implementation .. 17 Chapter 5: Example DesignOverview .. 18 Implementing the Example Design .. 19 Example Design Directory Structure .. 19 Simulating the Example Design.. 20 Chapter 6: Test BenchAppendix A: Migrating and UpgradingMigrating to the Vivado Design Suite .. 22 Upgrading in the Vivado Design Suite .. 22 Send FeedbackAXI UART Lite April 5, 2017 Appendix B: DebuggingFinding Help on.
peripheral. • Transmits and receives 8, 7, 6, or 5-bit characters, with one stop bit and with odd, even, or no parity bit. The AXI UART Lite can transmit and receive independently. • Generates a rising-edge sensitive interrup t when the receive FIFO becomes non-empty or when the transmit FIFO becomes empty. This interrupt can be masked by ...
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