Transcription of AXI4-Stream FIFO v4 - Xilinx
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AXI4-Stream FIFO v4 - Xilinx
AXI4-Stream fifo IP Product GuideVivado Design SuitePG080 April 6, 2016 AXI4-Stream fifo April 6, 2016 Table of ContentsIP FactsChapter 1: OverviewApplications .. 6 Unsupported Features .. 6 Licensing and Ordering Information .. 6 Chapter 2: Product SpecificationStandards .. 7 Performance .. 7 Resource Utilization .. 9 Port Descriptions .. 9 Register Space .. 19 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 33 Clocking.. 34 Resets .. 34 Protocol Description .. 34 Programing Sequence .. 36 Chapter 4: Design Flow StepsCustomizing and Generating the Core.
more details, see AXI Ethernet Subsystem Product Guide [Ref 4]. The AXI4-Stream FIFO core uses one clock from the AXI4-Lite interface for all clock inputs. When the AXI Ethernet core is used with the AXI4-Stream FIFO core, all the AXI Stream input clocks of the AXI Ethernet core must use the same clock. Table 2-3: I/O Signals
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