Transcription of AXI4-Stream FIFO v4 - Xilinx
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AXI4-Stream FIFO v4 - Xilinx
AXI4-Stream fifo IP Product GuideVivado Design SuitePG080 April 6, 2016 AXI4-Stream fifo April 6, 2016 Table of ContentsIP FactsChapter 1: OverviewApplications .. 6 Unsupported Features .. 6 Licensing and Ordering Information .. 6 Chapter 2: Product SpecificationStandards .. 7 Performance .. 7 Resource Utilization .. 9 Port Descriptions .. 9 Register Space .. 19 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 33 Clocking.. 34 Resets .. 34 Protocol Description .. 34 Programing Sequence .. 36 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 42 Constraining the Core.
• Configurable data width of 32, 64, 128, 256 or 512 bits (AXI4 Data Interface only). For AXI4-Lite, the FIFO data width is 32 bits and for AXI4, it is identical to AXI4 data width. • Configurable FIFO depth of 512 to 128k locations. • Independently configurable internal TX and RX data FIFOs • Full duplex operation
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