Transcription of AXI4-Stream FIFO v4 - Xilinx
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AXI4-Stream FIFO v4 - Xilinx
AXI4-Stream fifo IP Product GuideVivado Design SuitePG080 April 6, 2016 AXI4-Stream fifo April 6, 2016 Table of ContentsIP FactsChapter 1: OverviewApplications .. 6 Unsupported Features .. 6 Licensing and Ordering Information .. 6 Chapter 2: Product SpecificationStandards .. 7 Performance .. 7 Resource Utilization .. 9 Port Descriptions .. 9 Register Space .. 19 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 33 Clocking.. 34 Resets .. 34 Protocol Description .. 34 Programing Sequence .. 36 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 42 Constraining the Core.
This core does not support asynchronous clock (independent clock) mode. ... Table 2-2 show the throughput numbers for store-and-forward mode and cut-through mode. Clock frequency is kept constant at 100 MHz to calculate the throughput. ... gives the address of the first transfer in a write burst transaction. The
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