Transcription of AXI4-Stream FIFO v4 - Xilinx
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AXI4-Stream FIFO v4 - Xilinx
AXI4-Stream fifo IP Product GuideVivado Design SuitePG080 April 6, 2016 AXI4-Stream fifo April 6, 2016 Table of ContentsIP FactsChapter 1: OverviewApplications .. 6 Unsupported Features .. 6 Licensing and Ordering Information .. 6 Chapter 2: Product SpecificationStandards .. 7 Performance .. 7 Resource Utilization .. 9 Port Descriptions .. 9 Register Space .. 19 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 33 Clocking.. 34 Resets .. 34 Protocol Description .. 34 Programing Sequence .. 36 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 42 Constraining the Core .. 46 Simulation .. 46 Synthesis and Implementation .. 46 Appendix A: Verification, Compliance, and InteroperabilitySimulation .. 47 Hardware Testing .. 47 Appendix B: DebuggingFinding Help on .. 48 Send FeedbackAXI4-Stream fifo April 6, 2016 Debug Tools .. 49 Simulation Debug.. 50 Hardware Debug .. 50 Appendix C: Migrating and UpgradingMigrating to the Vivado Design Suite.
Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative. ... (MBytes/sec) Store-and-Forward Mode Cut-Through Mode AXI4-Lite 100 8 KB 64.88 77.51 AXI4 100 8 KB 198.49 393.65 Table 2-2: AXI4-Stream FIFO Receive Throughput
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