Basic Verilog

1 Part 3: Verilog : Hardware Organization and DesignECE 232 Verilog tutorial2 Basic Verilogmodule <module_name> (<module_terminal_list>); <module_terminal_definitions>..<functionality_of_module>..endmoduleEngin 112 Verilog examples: 353 Verilog Resources 667 Verilog (on the left side menu): 232 Verilog tutorial3 Full Addermodule FullAdder(a,b,cin,cout,sum);input a, b, cin; // inputsoutput cout, sum; // outputwire w1, w2, w3, w4; // internal netsxor#(10) (w1, a, b); // delay time of 10 unitsxor#(10) (sum, w1, cin); and #(8) (w2, a, b);and #(8) (w3, a, cin);and #(8) (w4, b, cin);or #(10, 8)(cout, w2, w3, w4); // (rise time of 10, fall 8)endmoduleabcincoutsum ECE 232 Verilog tutorial4 Multiple ways of implementing Full Addermodule FullAdder(a,b,cin,sum,cout);input a,b,cin; output sum, cout; reg sum, cout; // registers retain valuealways @ (a or b or cin) // Anytime a or b or cinCHANGE, run the process begin sum <= a ^ b ^ cin.

Hardware description languages (HDL) offer a way to design circuits using text-based descriptions HDL describes hardware using keywords and expressions. Representations for common forms »Logic expressions, truth tables, functions, logic gates Any combinational …

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