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全差分运算放大器设计 - big-bit.com

VLSI 2003 12 31 : , 1 (011021361) (021021061) CMOS 2P2M z : >80dB z : >50 MHz z : =5pF z : >60 z : >12dB z : >200Vs z : (VDD=5V) z : >10 MHz z : 20nVHz z : <10mV z : > 4V Vin+Vin-Vb1Vo-Vo+Vb3Vb2 CCRCCCRCM1M2M3M4M5M6M7M8M11M12M9M10 VcmfbM13 CLCL 1 VLSI 2003 12 31 : , 2 : (a) two-stage (b) folded - cascode ; (c) tel

folded-cascode; (c)共源共栅，telescopic。该运算放大器的设计指标要求差分输出摆幅为±4V， 即输出端的所有NMOS 管的VDSAT N, 之和小于0.5V，输出端的所有PMOS 管的VDSAT P, 之和也必须 小于0.5V。对于单级的折叠共源共栅和直接共源共栅两种结构，都比较难达到该要求，因此我

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