Transcription of Board Design Guidelines for PCI Express™ Architecture
{{id}} {{{paragraph}}}
Example: stock market
Board Design Guidelines for PCI Express™ Architecture
Board Design Guidelines for PCI Express Architecture Zale Schoenborn Co-Chair, PCI Express Electrical WG. Copyright 2004, PCI-SIG, All Rights Reserved 1. Agenda Background Layout considerations System Board requirements Add-in card designs Signal validations Summary PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 2. Background T/s Bus Topology Evolution 133. M. CONN. CONN. MCH. PCI common clock Meet setup/hold timing CLK. Multi-drop parallel I/O T/s M. 533. AGP source synchronous CONN. Single strobe, multiple data MCH. Match all data to strobes T/s PCI Express serial differential +G. Embedded clock CONN. MCH. Point-to-point, match per data pair only Longer route, creative device placement PCI. PCI Express Express pt-to-pt pt-to-pt routing routing is is straightforward straightforward PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 3.
Example VNA measurements for differential mstrip trace insertion loss -5.23dB 1.25GHz 20-inch line freq dB Layout considerations. ... level retention solutions “Hockey-stick” to allow for new retention solutions Fixed height for I/O cards (allowance for low profile compliance)
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: