Transcription of CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES
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CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES
PRINTER CIRCUIT BOARD ISSUES CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES INTRODUCTION SECTION : PARTITIONING SECTION : TRACES RESISTANCE OF CONDUCTORS VOLTAGE DROP IN SIGNAL LEADS "KELVIN FEEDBACK" SIGNAL RETURN CURRENTS GROUND NOISE AND GROUND LOOPS GROUND ISOLATION TECHNIQUES STATIC PCB EFFECTS SAMPLE MINIDIP AND SOIC OP AMP PCB GUARD LAYOUTS DYNAMIC PCB EFFECTS INDUCTANCE STRAY INDUCTANCE MUTUAL INDUCTANCE PARASITIC EFFECTS IN INDUCTORS Q OR "QUALITY FACTORS" DON'T OVERLOOK ANYTHING STRAY CAPACITANCE CAPACITATIVE NOISE AND FARADAY SHIELDS BUFFERING ADCs AGAINST LOGIC NOISE HIGH CIRCUIT IMPEDANCES ARE SUSCEPTIBLE TO NOISE PICKUP SKIN EFFECT TRANSMISSION LINES DESIGN PCBs
BASIC LINEAR DESIGN 12.4 Figure 12.1: Analog and Digital Circuits Should Be Partitioned on PCB Layout The layout of the evaluation board is optimized in terms of grounding, decoupling, and signal routing and can be used as a model when laying out the ADC section of the PC
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