Chapter 9 Design Constraints and Optimization

OverviewConstraints are used to influence the FPGA Design implementation tools including the synthesizer, and place-and-route tools. They allow the Design team to specify the Design performance requirements and guide the tools toward meeting those requirements. The implementation tools prioritize their actions based on the Optimization levels of synthesis, specified timing, assignment of pins, and grouping of logic provided to the tools by the Design team. The four primary types of Constraints include synthesis, I/O, timing and area/location Constraints influence the details of how the synthesis of HDL code to RTL occurs.

141 Design Constraints and Optimization On-chip routing resources Required logic speed versus maximum FPGA speed Required logic speed versus layers of logic required to implement the design Pin assignment can also become critical at the board level when signals require special routing considerations such as short signal trace length, matched line length, or controlled

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