Transcription of Chapter 9 Design Constraints and Optimization - Elsevier.com
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Chapter 9 Design Constraints and Optimization - Elsevier.com
OverviewConstraints are used to influence the FPGA Design implementation tools including the synthesizer, and place-and-route tools. They allow the Design team to specify the Design performance requirements and guide the tools toward meeting those requirements. The implementation tools prioritize their actions based on the Optimization levels of synthesis , specified timing, assignment of pins, and grouping of logic provided to the tools by the Design team. The four primary types of Constraints include synthesis , I/O, timing and area/location Constraints influence the details of how the synthesis of HDL code to RTL occurs.
There are two categories of register balancing and they are referred to as forward and backward balancing. Forward register balancing seeks to move a set of registers located at a LUT’s input to a single register at the LUT’s output. Backward regis-ter balancing is based on the opposite principle. The synthesis tool works to move a register
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