Transcription of CMOS Capacitance and Circuit Delay
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CMOS Capacitance and Circuit Delay
Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 CMOS Capacitance and Circuit DelayA) CMOS Structure and CapacitanceB) Gate and Source Drain Capacitance ModelC) Cascade Inverter DelayD) Capacitance from Logic FunctionE) Fan-Out and Logic DelayReading: Schwarz and Oldham, pp. 518-526, and lectures 16-19. Lecture 24 Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Dynamic Performance: Add CapacitancesCapacitance CGis between gate and the underlying channel, which is connected to the source, CGS= CG and hence is modeled as Capacitance to LWCC= =LWArea of GateWCLWCC perimeterjunctionSD + =min4 Capacitance CSDhas a bottom and out-side perimeter between the source or drain and the underlying substrate which is connected to ground.
Capacitance CSD has a bottom and out-side perimeter between the source or drain and the underlying substrate which is connected to a.c. ground. There is also a gate perimeter component for which there is a 2X magnifying (Miller) effect on the S/D side because the
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