Transcription of Combinational Logic Circuits - Clemson University
{{id}} {{{paragraph}}}
Combinational Logic Circuits CPSC 855 Embedded Systems Fryad M. Rashid and Pei-Lin Chung Outline Design Combinational Logic Circuit for scenario Adder Subtractor Comparator Multiplexer Demultiplexer Encoder Decoder Code Conversions Implementation Design Methods Type of IC chips (based on packing density) : Small-scale integration (SSI): up to 12 gates Medium-scale integration (MSI): 12-99 gates Large-scale integration (LSI): 100-9999 gates Very large-scale integration (VLSI): 10,000-99,999 gates Ultra large-scale integration (ULSI): > 100,000 gates Main objectives of circuit design: (i) reduce cost reduce number of gates (for SSI Circuits ) reduce IC packages (for complex Circuits ) (ii) increase speed (iii) design simplicity (reuse blocks where possible) Application of CLC Introduction Combinational Logic Circuits ( Circuits without a memory): In this type of Logic Circuits outputs depend only
The simplified Boolean function for each output is obtained (using K-Map, Tabulation method and Boolean Algebra rules). 6. The logic diagram is drawn.! To design a combinational logic circuit use the following procedures:
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document:
{{id}} {{{paragraph}}}