Transcription of Data Sheet: MAX 7000 Programmable Logic Device …
{{id}} {{{paragraph}}}
Example: bachelor of science
Data Sheet: MAX 7000 Programmable Logic Device …
Altera Corporation 1 MAX 7000 Programmable LogicDevice FamilySeptember 2005, ver. High-performance, EEPROM-based Programmable Logic devices (PLDs) based on second-generation MAX architecture in-system programmability (ISP) through the built-in IEEE Std. Joint Test Action Group (JTAG) interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532 Includes MAX 7000 devices and ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells Complete EPLD family with Logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin Logic delays with up to counter frequencies (including interconnect) PCI-compliant devices availablefFor information on in-system Programmable MAX 7000
2 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet...and More Features Open-drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50% in each macrocell
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: