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DESIGN OF SINGLE PRECISION FLOAT ADDER (32-BIT …

MASTER THESIS. DESIGN OF SINGLE . PRECISION FLOAT ADDER . (32-BIT NUMBERS). ACCORDING TO IEEE 754. STANDARD USING vhdl . Arturo Barrab s Castillo Bratislava, April 25th 2012. Supervisors: Dr. Roman Z lusky Prof. Viera Stopjakov . Fakulta Elecktrotechniky a Informatiky Slovensk Technick Univerzita v Bratislave INDEX. Index ..3. Zhrnutie ..5. Abstract ..5. Chapter 1: 7. Floating Point Numbers ..7. The Standard IEEE 754 ..8. Overview ..8. Binary Interchange Format Encodings ..9. PRECISION and Rounding ..10. Chapter 2: Code Development .. 13. 32-bits Floating Point ADDER DESIGN ..13. Addition/Subtraction Steps.

MASTER THESIS DESIGN OF SINGLE PRECISION FLOAT ADDER (32-BIT NUMBERS) ACCORDING TO IEEE 754 STANDARD USING VHDL Arturo Barrabés Castillo Bratislava, April 25 th 2012 Supervisors: Dr. Roman Zálusky

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