Transcription of DESIGN OF SINGLE PRECISION FLOAT ADDER (32-BIT …
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DESIGN OF SINGLE PRECISION FLOAT ADDER (32-BIT …
MASTER THESIS. DESIGN OF SINGLE . PRECISION FLOAT ADDER . (32-BIT NUMBERS). ACCORDING TO IEEE 754. STANDARD USING VHDL. Arturo Barrab s Castillo Bratislava, April 25th 2012. Supervisors: Dr. Roman Z lusky Prof. Viera Stopjakov . Fakulta Elecktrotechniky a Informatiky Slovensk Technick Univerzita v Bratislave INDEX. Index ..3. Zhrnutie ..5. Abstract ..5. Chapter 1: 7. floating Point Numbers ..7. The Standard IEEE 754 ..8. Overview ..8. Binary Interchange Format Encodings ..9. PRECISION and Rounding ..10. Chapter 2: Code Development .. 13. 32-bits floating Point ADDER DESIGN ..13. Addition/Subtraction Steps ..13. Block Blocks Pre- ADDER DESIGN ..17. ADDER DESIGN ..17. Standardizing DESIGN ..19. Chapter 3: 21. Special n_case Subnormal Numbers ..25. n_subn Block ..25. Mixed Numbers ..27. comp Block ..27. zero Block ..30. shift_left/shift Block ..32. norm Block ..35. Normal Numbers ..38. comp_exp Block ..38. shift Block ..41.
Floating Point Arithmetic represent a very good compromise for most numerical applications. 1.1. Floating Point Numbers The floating point numbers representation is based on the scientific notation: the decimal point is not set in a fixed position in the bit sequence, but its position is indicated as a base power.
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