Transcription of DS093: XC2C128 CoolRunner-II CPLD Specification
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DS093: XC2C128 CoolRunner-II CPLD Specification
DS093 ( ) March 8, Specification 2002-2007 xilinx , Inc. All rights reserved. All xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without Optimized for systems-As fast as ns pin-to-pin delays-As low as 13 A quiescent current Industry s best micron CMOS CPLD-Optimized architecture for effective logic synthesis -Multi-voltage I/O operation to Available in multiple package options-100-pin VQFP with 80 user I/O-144-pin TQFP with 100 user I/O-132-ball CP ( ) BGA with 100 user I/O-Pb-free available for all packages Advanced system features-Fastest in system programming ISP using IEEE 1532 (JTAG) JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)-Unsurpassed low power management DataGATE enable (DGE) signal control-Two separate I/O banks-RealDigital 100% CMOS product term generation-Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide by 2,4,6,8,10,12,14,16)
XC2C128 CoolRunner-II CPLD 2 www.xilinx.com DS093 (v3.2) March 8, 2007 Product Specification R By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.
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