dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Data Sheet

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 . 16-bit Digital Signal Controllers (up to 32 KB Flash and 2 KB SRAM) with motor control and Advanced Analog Operating Conditions Six analog inputs on 28-pin devices and up to nine analog inputs on 44-pin devices to , -40 C to +150 C, DC to 20 MIPS. Flexible and independent ADC trigger sources to , -40 C to +125 C, DC to 40 MIPS. Timers/Output Compare/Input Capture Core: 16-bit dsPIC33F CPU. Three 16-bit timers/counters. Can pair up two to Code-efficient (C and Assembly) architecture make one 32-bit. Two 40-bit wide accumulators Two Output Capture modules configurable as Single-cycle (MAC/MPY) with dual data fetch timers/counters Single-cycle mixed-sign MUL plus hardware divide Four Input Capture modules Peripheral Pin Select (PPS) to allow function Clock Management remap 2% internal oscillator Communication Interfaces Programmable PLLs

Remappable Pins 16-bit Timer Input Capture Output Compare Standard PWM Motor Control PWM Quadrature Encoder Interface UART External Interrupts C™ I/O Pins Packages (3) SPI dsPIC33FJ32MC202 28 32 2 16 3(1) 426ch(2) 2ch(2) 1 1 3 1 1ADC, 6 ch 121SPDIP SOIC SSOP QFN-S dsPIC33FJ32MC204 44 32 2 26 3(1) 426ch(2) 2ch(2) 1 1 3 1 1ADC, 9 ch 135 QFN TQFP

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  Control, Motor, Motor control, Dspic33fj32mc202 204 and dspic33fj16mc304, Dspic33fj32mc202, Dspic33fj16mc304

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