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ECE 128 Synopsys Tutorial: Using the Design Compiler ...

ECE 128 Synopsys Tutorial: Using the Design Compiler Created at GWU by Thomas Farmer Updated at GWU by William Gibb, Spring 2010 Updated at GWU by Thomas Farmer, Spring 2011 Objectives: Synthesize a structural 1-bit full adder Using the Synopsys Design Compiler Synthesize a behavioral 1-bit full adder Using the Synopsys Design Compiler Synthesize both full adders Using the AMI .5 library Using the OSU Standardized Cells Assumptions: Student has completed lab 1 and has a working structural 2-bit full adder Introduction: The ASIC Design flow is as follows: Specification RTL Coding and Simulation Logic Synthesis Optimization Gate Level Simulation Static Timing Analysis Place and Route Static Timing Analysis Preliminary Netlist Handoff In this tutorial, we will be working in Logic Synthesis portion of the ASIC flow.

5) Load all your verilog code (and its dependent files) by going to: File->Analyze Click on the “add” button and click on the “src” sub-directory Add “fulladder.v” and “halfadder.v” Note : The analyze command will do syntax checking and create intermediate .syn files which will be stored in the directory work, the defined design library.

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