Transcription of ECEN720: High-Speed Links Circuits and Systems Spring 2021
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ECEN720: High-Speed Links Circuits and Systems Spring 2021
Sam PalermoAnalog & Mixed-Signal CenterTexas A&M UniversityECEN720: High-Speed Links Circuits and SystemsSpring 2021 Lecture 12: CDRsAnnouncements Lab 6 due Apr 12 Project Preliminary Report due Apr 19 Project Final Report due Apr 292 Agenda CDR overview CDR phase detectors Single-loop analog PLL-based CDR Dual-loop CDRs Phase interpolators CDR jitter properties3 Embedded Clock I/O Circuits4 TX PLL TX Clock Distribution CDR Per-channel PLL-based Dual-loop w/ Global PLL & Local DLL/PI Local Phase-Rotator PLLs Global PLL requires RX clock distribution to individual channelsClock and Data Recovery A clock and data recovery system (CDR) produces the clocks to sample incoming data The clock(s) must have an effective frequency equal to the incoming data rate 10 GHz for 10Gb/s data rate OR, multiple clocks spaced at 100ps Additional clocks may be used for phase detection Sampling clocks should have the proper phase relationship with the incoming data for sufficient timing margin to achieve the desired bit-error-rate (BER) CDR should exhibit small effective jitter5[Razavi]6 Embedded Clocking (CDR)early/lateVCTRL integral gainproportional gainDinLoop FilterRX[n:0]FSMselearly/latePhase-Recov ery LoopRXPDCPV ctrlFrequencySynthesisPLL5-stage coupled VCO4800 MHZ Ref C
pumps minimize logic and loop delay [Roshan-Zamir JSSC 2019] Charge Pump Early Late Loop Filter I Q QB IB D n[1:3] E n 12 4 2X Oversampling Clock Generators In 4:8 24 8 PAM4 BBPD CML Divider CML to CMOS I Q CLK0 CLK45 CLK90 Phase Calibration Data CLK Edge CLK 4 4 4 4 VCNT 14 GHz LC-VCO
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